The present invention relates to bit configuration of a bus, and in particular to methods and apparatuses for dynamically determining bit configuration for a host bridge.
Peripheral Component Interconnect (PCI) Express bus is an interconnection system between a microprocessor and attached devices. The PCI Express bus serves as a standard architecture for system bus. Presently, microprocessors and attached devices demand higher bandwidth system buses to support both frequency and voltage requirements. Due to PCI Express bus support for both frequency and voltage requirements, PCI Express bus will play a major role in the foreseeable future.
PCI Express bus utilizes flat memory address mapping to access device configuration registers, that is, the memory address determines the bit configuration of the system bus for a host bridge. According to the specifications for PCI Express bus, for example PCI Express Base specification rev. 1.0, PCI 2.3 Compatible Configuration Mechanism, or PCI Express Enhanced Configuration Mechanism, the bit configuration is defined as shown in Table 1. In table 1, “A” represents memory address.
TABLE 1Memory AddressPCI Express bit configurationA[20]-A[27]Bus number fieldA[15]-A[19]Device number fieldA[12]-A[14]Function number field A[8]-A[11]Extended register number fieldA[2]-A[7]Register number fieldA[0]-A[1]Along with size of the access, usedto generate byte enables
As shown in Table 1, from A[0] to A[27], a PCI Express bus requires a 256 MB (228 megabyte) based memory address allocation. Thus, a system may implement at least 28 pins for PCI Express bus architecture. Some systems, such as mini or closed systems, may adopt PCI Express bus as system architecture without providing as many pins.
Additionally, as previously mentioned, PCI Express bus adopts a 256 MB based memory address allocation. The limitation of memory address allocation may cause memory allocation fragments. Some systems, such as Root Complex systems or multi-Root Complex systems, may release the limitation of memory address allocation for system efficiency. However, present methods and systems cannot resolve previously mentioned problems.